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smm605 preliminary information 1 (see last page) ? summit microelectronics, inc. 2003 ? 757 n. mary avenue ? sunnyvale ca 94085 ? phone 408 523-1000 ? fax 408 523-1266 http://www.summitmicro.com 2064 2.1 12/16/2011 1 features & application introduction ? extremely accurate (0.2%, typ.) active dc output control ? six-channel control of dc/dc converters ? adoc automatically adjusts supply output voltage level under all dc load conditions ? capable of margining supplies with trim inputs using either positive or negative trim pin control ? wide margin/adoc range from 0.35v to vdd ? uses either an internal or external vref ? operates from any intermediate bus supply from 6v to 14v and vdd from 2.7v to 5.5v ? programmable start and ready pins ? general purpose 4k eeprom with write protect ? i 2 c 2-wire serial bus for programming configuration and monitoring status. ? 48-lead tqfp package applications ? monitor/control distributed and pol supplies ? multi-voltage processors, dsps, asics used in telecom, compactpci or server systems the smm605 actively controls the output voltage level of up to six dc/dc converters that use a ?trim? or ?vadj/fb? pin to adjust the output. an active dc output control (adoc tm ) feature is used during normal operation to maintain extremely accurate settings of supply voltages and, during system test, to control margining of the supplies using the industry standard i 2 c 2-wire data bus commands. total accuracy with a 0.1% external reference is 0.2%, and 0.5% using the internal reference. the device can margin supplies with either positive or negative trim pin control within a range of 0.35v to vdd. the smm605 supply can range from 2.7v to 5.5v or 6v to 14v to accommodate any intermediate bus supply. the voltage settings (margin high/low and nominal) are programmed into nonvolatile memory. the i 2 c bus is used to enable margin high, margin low, adoc or normal operation. when marg ining, the smm605 will check the voltage output of the converter and make adjustments to the trim pin via a feedback loop to bring the voltage to the margin setting. a margining status register is set to indicate that the system is ready for test. six-channel supply voltage marginer and active dc output controller (adoc tm ) simplified applications drawing trim b vm b trim_cap b trim a vm a trim_cap a smm605 p/ asic vdd ready 3.3vin (+2.7v to +5.5v range) ready 12vin 12vin (+6v to +14v range) 2.5vin 1.2vin 12v sda scl i 2 c bus 3.3v a2 vref_cntl vin trim vout dc/dc converter a vin trim vout dc/dc converter b external or internal reference dc/dc converter c, e dc/dc converter d, f 2 of 6 dc-dc converters shown start power good vdd_cap figure 1 ? applications schematic using the smm605 c ontroller to actively control and margin the output levels of up to six dc/dc converters. note: this is an applications example only. some pins, components and values are not shown.
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 2 general description the smm605 is capable of controlling the dc output of up to six dc/dc modules, switching regulators or ldos that use a trim/adjust pin and automatically change the level using a unique active dc output control (adoc tm ). the adoc function is programmable over a standard 2-wire i 2 c serial data interface and can be used to set the nominal dc output voltage as well as the margin high and low settings. the part actively controls the programmed set levels to maintain tight control over load variations and voltage drops at the point of load. the margin range will vary depending on the supply manufacturer and model but the normal range is 10% adjustment around the nominal output setting. however, the smm605 has the capability to margin from 0.35v to vdd. the user can set the desired voltage settings (nominal, margin high and margin low) into the ee memory array for the device. then, volatile registers are used to select one of these settings. these registers are accessed over the i 2 c bus. in normal operation, active dc output control is set to adjust the nominal output voltage of the converter. typical converter accuracy ratings range from 2% to 5% of their output voltage. using the active dc output control feature of the smm605 can increase the accuracy to 0.1% ( 0.2% max.). this high accuracy control of the converter output voltage is extremely important in low voltage applications where deviations in power supply voltage can result in lower system performance. active dc output control can also be used for margining a supply during system test or may be turned off by de-selecting the function in the control register. the margin high and margin low voltage settings can range from 0.35v to vdd around the converters? nominal output voltage setting depending on the specified margin range of the dc-dc converter. when the smm605 receives the command to margin, the active dc output control will adjust the supply to the selected margin voltage. once the supply has reached its margined set point, the ready bit in the status register will set and the ready pin will go active. if active dc control is disabled, a margined supply can return to its nominal voltage by writing to the margin command register. in order to obtain maximum accuracy, the smm605 requires an external voltage reference. an external reference with 0.1% accuracy will enable an overall 0.2% accuracy for the device. a configuration option also exists so that an internal voltage reference can be used, but with less accuracy. total accuracy using the internal reference is 0.5%. the smm605 has additional filter pins to filter unwanted switching regulator noise. they are vdd_cap and filt_cap. the smm605 can be powered from either the 12vin supply pin (6v to 14v range) via an internal regulator or the vdd supply pin (+2.7 to 5. 5v range), see figure 3. programming of the smm605 is performed over the industry standard i 2 c 2-wire serial data interface. a status register is available to read the state of the part and a write protect bit is available to prevent writing to the configuration registers and ee memory. figure 2 ? example power supply margining using the smm 605. the waveform on the left is margin low to high from 1.6v to 2.0v and the waveform on the right is margin high to nominal from 2.0v to 1.8v. the adoc function guarantees the output level to be within 0.2% maximum with a 0.1% external reference. the bottom waveform is the ready signal indicating margin is complete.
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 3 output control trim drive trim drive trim drive trim drive trim drive trim drive input voltage sensing and signal conditioning a2 sda scl vref_cntl vout trima trim_capa trimf trim_capf filt_cap v+ v- vma vmf ready 12vin vdd 3.6v or 5.5v regulator power supply arbitrator vdd_cap control logic start 1:6 mux 6:1 mux level shift ee memory figure 3 ?smm605 internal functional block diagram. internal functional block diagram
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 4 pin number 1 pin type pin name pin description 41 in vm a voltage monitor pin. connect to the dc-dc converter + sense line or + vout pin. 36 vm b 31 vm c 26 vm d 21 vm e 16 vm f 44 out trim a output voltage used to margin and/or trim converter voltages. connect to the converter trim input or to the vadj or fb pin of an adjustable output switching regulator or ldo through a resistor. if the adoc/margining functionality is not used on a channel, the associated trimx pin should be floating. 39 trim b 34 trim c 29 trim d 24 trim e 19 trim f 45 i/o trim_cap a external sample and hold capacitor input used to set the voltage on the trim pins. 40 trim_cap b 35 trim_cap c 30 trim_cap d 25 trim_cap e 20 trim_cap f 48 in vdd_cap external capacitor input used to f ilter the internal supply rail. 47 pwr 12vin 12v power supply input internally regulat ed to 3.6 or 5.5v. input range is 6v to 14v using the 3.6v internal regulator setting and 10v to 14v using the 5.5v internal regulator setting. 46 pwr vdd 2.7v to 5.5v power supply of the part. 5, 6, 12, 13 gnd gnd ground of the part. pin descriptions
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 5 pin number pin type pin name pin description 15 in filt_cap external capacitor input used to filter vm x inputs. this provides an rc filter where r = 1k ? . 14 in vref_cntl voltage reference input used for dc output control and margining. 1 i/o sda bi-directional i 2 c data line. 2 in scl i 2 c clock line. 3 in a2 the address pin is biased either to vdd_cap or gnd. when communicating with the smm605 over the 2-wire bus a2 provides a mechanism for assigning a unique bus address. 4 in start programmable active high/low input. the start input is used solely for enabling active control and/or margining. 7 out ready programmable active high/low open drain output signals indicating when all programmed power supplies have reached their preprogrammed setpoints. nc no connect leave the nc pins floating. package and pin configuration 48 lead tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 ldo# wdo# crowbar 1.25vref mr# irq_clr# irq# pgnd trkr_irq# seated1# uv_ovrride seated2# cb2 cb3 cb4 pwr_on vgate1 vgate2 vgate3 vgate4 vgg_cap force_sd cbfault healthy# wldi scl sda a2 a1 a0 vdd_cap vi1 vi2 vi3 cb1 vi4 rst1# rst2# rst3# rst4# pgnd dgnd agnd vo1 vo2 v03 enable vo4 pin descriptions (cont.)
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 6 absolute maximum ratings temperature unde r bias ...................... -55 c to 125 c storage temper ature ............................ -65 c to 150 c terminal voltage with respect to gnd: vdd supply voltage .......................... -0.3v to 6.0v 12vin suppl y voltage ...................... -0.3v to 15.0v all others ................................ -0.3v to v dd + 0.7v output short circ uit current ............................... 100ma lead solder temperature (10 secs) . ?????300 c junction temperature........ ...............?? .....?...150c esd rating per jedec?? ??????..?..2000v latch-up testing per jedec???..??....? 100ma recommended operating conditions temperature range (industrial) ........... ?40 c to +85 c (commercial) ............ ?5 c to +70 c vdd supply voltage .................................. 2.7v to 5.5v 12vin supply voltage 1 ............................ 6.0v to 14.0v vin ............................................................ gnd to vdd vout ...................................................... gnd to 14.0v package thermal resistance ( ja ) 48-lead tqfp????????????.?80 o c/w moisture classification level 1 (m sl 1) per j-std- 020. msl 3 for 100% sn, rohs compliant, see ordering information. dc operating characteristics (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) s y mbol paramete r notes min t yp max unit vdd supply voltage 2.7 5.5 v 12vin supply voltage internally regulated to 5.5v 10 14 v internally regulated to 3.6v 6 14 v i dd power supply current from vdd all trim pins floating, 12vin floating 3 5 ma i 12vin power supply current from 12vin all trim pins floating, vdd floating 3 5 ma trim characteristics i trim trim output current through 100 to 1.0v trim sourcing maximum current 1.5 ma trim sinking maximum current 1.5 ma v trim margin control and adoc range depends on trim range of dc-dc converter vref_cnt l/4 vdd v all other input and output characteristics v dd_cap vdd_cap voltage internally regulated to 3.6v 3.4 3.6 3.8 v internally regulated to 5.5v 5.3 5.5 5.7 v no voltage on 12vin vdd ? 0.1 vdd vdd + 0.1 v v ih input high voltage (fs, sda, scl, pwr_on/off) 2 vdd = 2.7v 0.7 x vdd_cap v vdd = 5.0v 0.7 x vdd_cap v v il input low voltage (fs, sda, scl, pwr_on/off) 2 vdd = 2.7v 0.3 x vdd_cap v vdd = 5.0v 0.3 x vdd_cap v note - the device is not guaranteed to function outside its oper ating rating. stresses listed under absolute maximum ratings ma y cause permanent damage to the device. these are stress ratings only and functional operation of the devic e at these or any other con ditions outside those listed in the operational sections of the specification is not implied. exposu re to any absolute maximum rating for exte nded periods may affect device performance and reliability. devices are esd sensitive. handling precautions are recommended.
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 7 dc operating characteristics (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter notes min typ. max unit v ih input high voltage (fs, sda, scl, pwr_on/off) 2 internally regulated to 3.6v 0.7 x vdd_cap v internally regulated to 5.5v 0.7 x vdd_cap v v ih input high voltage (fs, sda, scl, pwr_on/off) 2 internally regulated to 3.6v 0.3 x vdd_cap v internally regulated to 5.5v 0.3 x vdd_cap v i ol output low current 3 note ? total i sink from all pupx pins should not exceed 6ma or adoc acc specification will be affected 0 1.0 ma i olsda output low current for sda vol=0.4v 3 ma i s leakage current on sda and scl sda or scl are at 3.6v 1.0 a v sense positive sense voltage vm pins +0.35 vdd_cap v v monitor monitor threshold step size vm pins 5 mv v ref internal 1.25v ref output voltage accuracy t = +25 c -0.4 +0.4 % t = -40 c to +85 c -0.8 +0.8 % external v ref external v ref voltage range 0.5 vdd_cap v adoc acc adoc/margin accuracy external v ref =1.25v, 0.1%, total pupx i sink = 6ma, v sense 3.5v, t = 0 c to +50 c -0.20 0.1 +0.20 % external v ref =1.25v, 0.1%, total pupx i sink = 6ma, v sense 3.5v, t = 0 c to +70 c -0.35 0.1 +0.35 % external v ref =1.25v, 0.1%, total pupx i sink = 6ma, v sense 3.5v, t = 0 c to +50 c -0.50 0.3 +0.50 % internal v ref =1.25v, total pupx i sink = 6ma, t = 0 c to +50 c -0.50 0.3 +0.50 % uvlo under voltage lockout threshold 4 vdd_cap rising 2.6 v vdd_cap falling 2.5 v i vdd-cap vdd_cap maximum output current vdd = 2.7v to 5.5v, internal reg = 3.6v or 5.5v 5 ma note 1 ? range depends on internal regulator set to 3.6v or 5.5v see 12vin specification. note 2 ? all logic levels are derived with respect to the volt age present on vdd_cap, when supplied from the vdd input vdd_cap is equal to vdd, under no load. note 3 ? sda not included (separat e electrical specification) note 4 ? (100mv typ hysteresis)
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 8 ac operating characteristics (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol description conditions min typ max unit t dc_control active dc control sampling period update period for active dc control of channels a ? f 1.7 ms t settling settling time + 10% change in voltage with 0.1% ripple 100 ms t margin margin time from nominal to 5% slow margin, f 850 ms fast margin, f 85 ms
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 9 i 2 c 2-wire serial interface ac operating characteristics ? 100/400khz over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd. see figure 4 timing diagram. symbol description conditions 100khz 400khz min typ max min typ max units f scl scl clock frequency 0 100 0 400 khz t low clock low period 4.7 1.3 s t high clock high period 4.0 0.6 s t buf bus free time before new transmission 5 4.7 1.3 s t su:sta start condition setup time 4.7 0.6 s t hd:sta start condition hold time 4.0 0.6 s t su:sto stop condition setup time 4.7 0.6 s t aa clock edge to data valid scl low to valid sda (cycle n) 0.2 3.5 0.2 0.9 s t dh data output hold time scl low (cycle n+1) to sda change 0.2 0.2 s t r scl and sda rise time note 5 1000 1000 ns t f scl and sda fall time note 5 300 300 ns t su:dat data in setup time 250 150 ns t hd:dat data in hold time 0 0 ns ti noise filter scl and sda noise suppression 100 100 ns t wr write cycle time 5 5 ms note 5 - guaranteed by design. t r t f t high t low t su:sta t hd:sta t su:dat t hd:dat t su:sto t buf t dh t aa scl sda (in) sda (out) t wr (for write operation only) figure 4 - basic i 2 c serial interface timing timing diagrams
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 10 applications information device operation power supply the smm605 can be powered by either a 6v to 14v input through the 12vin pin or by a 2.7v to 5.5v input through the vdd pin (figure 3). the 12vin pin feeds an internal programmable regulator that internally generates either 5.5v or 3.6v. the internal regulator must be set to 3.6v if using an 8v supply. a voltage arbitration circuit allows the device to be powered by the highest voltage from either the regulator output or the vdd input. this voltage arbitration circuit continuously checks for these voltages to determine which will power the smm605. the resultant internal power supply rail is connected to the vdd_cap pin that allows both filtering and hold-up of the internal power supply. voltage reference the smm605 can operate using either an internal or external voltage reference, vref. the internal vref is set to 1.25v. total accuracy with a 0.1% external reference is 0.2% and 0.5% using the internal reference. modes of operation the smm605 has two basic modes of operation: supply margining mode and active dc output control (adoc tm ). a detailed description of each mode and feature follows. active dc output control (adoc) the smm605 can actively control the dc output voltage of bricks or dc/dc c onverters that have a trim pin during monitoring and margining mode. the converter may be an off-the shelf compact device, or may be a ?roll your own? circuit on the application board. in either case, the smm605 dramatically improves voltage accuracy (down to 0.2%) by implementing closed-loop adoc active control. this utilizes the dc-dc?s ?trim? pin as shown in figure 7, or an equivalent output voltage feedback adjustment ?vadj? or ?fb? node in a user?s custom circuit, figure 8. each of the trim x pins on the smm605 is connected to the trim input pins on the power supply converters. a sense line from the channel?s point-of-load connects to the corresponding vm x input. the adoc function cycles through all six channels (a-f) every 1.7ms making slight adjustments to the voltage on the associated trim x output pins based on the voltage inputs on the vm x pins. these voltage adjustments allow the smm605 to control the output voltage of power supply converters to within 0.2% when using a 0.1% external voltage reference. the voltage on the trim_cap x pins is buffered and applied to the trim x pin. the voltage adjustments on the trim x pins cause a slight ripple of less than 1mv on the power supply voltage. the amplitude of this ripple is a function of the trim_cap x capacitor and the trim gain of the conver ter. calculation of the trim_cap x capacitor to achieve a desired minimum ripple is detailed in application note 37. the pulse of current can be increased to a 10x pulse of current until the power supply voltages are at their nominal settings by selecting the programmable fast convergence option. as the name implies, this option decreases the time required to bring a supply voltage from the converter?s nominal output voltage to the active dc output control nominal voltage setting. the device can be programmed to either enable or disable the active dc control function. when disabled or not active, the trim x pins on the smm605 are high impedance inputs. the voltage on the trim x pins are buffered and applied to the trim_cap x pins charging the capacitor. this allows a smooth transition from the converter?s nominal voltage to the smm605 controlling that voltage to the active dc control nominal setting. monitoring the smm605 monitors the vm x pins. the ready pin is programmable active high/low open drain output indicates that all vm x pins are at their set point.
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 11 applications information ( continued ) margining the smm605 has two additional active dc output control voltage settings: margin high and margin low. the margin high and margin low settings can be as much as 10% of the nominal setting depending on the manufacturer. the smm605 range can be as large as 0.35v to vdd. these settings are stored in the configuration registers and are loaded into the active dc output control voltage setting by margin commands issued via the i 2 c bus. the device must be enabled for active dc output control in order to enable margining. the margin command registers contain two bits that decode the commands to margin high, margin low, or control to the nominal setting. once the smm605 receives the command to margin the supply voltage, it begins adjusting the supply voltage to move toward the desired setting. when this voltage setting is reached, a bit is set in the margin status registers and the ready signal becomes active. (figure 2, 5 and 6) note: configuration writes or reads of registers 00 hex to 03 hex should not be performed while the smm605 is margining. write protection write protection for the smm605 is located in a volatile register where the power-on st ate is defaulted to write protect. there are separate write protect modes for the configuration registers and memory. in order to remove write protection, the code 55 hex is written to the write protection register. other codes will enable write protection. for example, writing 59 hex will allow writes to the configuration register but not to the memory, while writing 35 hex will allow writes to the memory but not to the configuration registers. in addition, there is a configuration register lock bit, which, once programmed, does not allow the configuration registers to be changed. figure 5 - margin high waveforms time/horizontal division = 200ms ch 1 (1v/div) = 3.3v dc-dc converter output (yellow trace) ch 2 (500mv/div) = 2.5vdc-dc converter output (blue trace) ch 3 (500mv/div) = 1.8v dc-dc converter output (purple trace) ch 4 (500mv/div) = 1.5v dc- dc converter output (green trace) figure 6 - margin low waveforms time/horizontal division = 400ms ch 1 (1v/div) = 3.3v dc-dc converter output (yellow trace) ch 2 (500mv/div) = 2.5v dc-dc converter output (blue trace) ch 3 (500mv/div) = 1.8v dc-dc converter output (purple trace) ch 4 (500mv/div) = 1.5v dc-dc converter output (green trace)
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 12 ready start j1 ext vref c6 1uf r4 10k r1 10k j1 1 2 3 4 5 6 7 8 9 10 gnd scl gnd3 sda rsrv5 mr +10v rsrv8 +5v rsrv10 r2 10k c6 0.1uf c8 0.1uf the smm605 and the dc-dc converter can operate with either 12v or vdd if 12v is used, vdd can be left floating if vdd is used, 12v can be left floating d1 diode if the smm605 internal vref is used, the vref_cntl pin becomes an output c4 0.1uf dc-dc enable +12vin (+6v to +14v) smx3200 i2c programming connector 10 pin header c1 0.1uf c2 0.1uf r3 10k u4 lm4121 1 2 3 4 5 ref gnd en vin vout c5 0.02uf u1 smm605 2 3 4 7 14 15 46 47 48 1 6 5 12 13 scl a2 start ready vref_cntl filt_cap vmx trim_capx trimx vdd 12vin vdd_cap sda gnd gnd gnd gnd vdd u2 dc-dc converter 1 2 3 4 5 6 7 8 9 10 11 +vout +vout sense +vout gnd gnd +vin +vin +vin trim enable c3 0.01uf vdd (+2.7v to +5.5v) vout j2 supply c7 0.01uf figure 7 ? smm605 applications schematic. the accuracy of the external (u4) or internal reference sets the accuracy of the adoc function. total accuracy with a 0.1% external reference is 0.2% and 0.5% with the internal reference. the 12v supply can go as low as 6v if the internal regulator is set to 3.6v. applications information (continued)
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 13 u2 lt3707 switching regulator +vout gnd +vin vosense pgood u1 smm605 2 3 4 7 14 15 46 47 48 1 6 5 12 13 scl a2 start ready vref_cntl filt_cap vmx trim_capx trimx vdd 12vin vdd_cap sda gnd gnd gnd gnd start c1 should be as close to the smm105 as possible c2 0.02uf r4 10k c4 0.1uf d1 diode c6 0.01uf the smm605 start pin must be inactive during power-up so that the trim pin is high impedence. once power is nominal, the start pin can be active to start margin and adoc functions r5 20k r2 10k c1 1uf j1 1 2 3 4 5 6 7 8 9 10 gnd scl gnd3 sda rsrv5 mr +10v rsrv8 +5v rsrv10 c3 0.1uf r5 10k start r4 rset1 vout vtrimlow=0.3v, vosense=0.8v the current through r3 is itrim=(0.8-0.3)/rtrim (itrim)(r4) > 15% of vout rtrimmax should be no greater then the calculated value ready for example, if vout=3.3v, r4=63.4k 15% of vout=0.5v itrim=8ua rtrim=62.5k so rtrim should be next value down from 62.5k c5 0.01uf r3 rtrim +12vin(+6v to 14v) smx3200 i2c programming connector 10 pin header r1 and r2 need only be placed once on the i2c bus r1 10k figure 8 ? smm605 applications schematic for an adjust able switching regulator (full regulator circuit not shown). applications information (continued)
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 14 figure 9 ? smm605 applications schematic. applications information (continued)
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 15 the end user can obtain the summit smx3200 programming system for device prototype development. the smx3200 system consists of a programming dongle, cable and windows tm gui software. it can be ordered on the website or from a local representative. the latest revisions of all software and an application brief describing the smx3200 is available from the website ( www.summitmicro.com ). the smx3200 programming dongle/cable interfaces directly between a pc?s par allel port and the target application. the device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. the windows gui software w ill generate the data and send it in i 2 c serial bus format so that it can be directly downloaded to the smm605 via the programming dongle and cable. an example of the connection interface is shown in figure 10. when design prototyping is complete, the software can generate a hex data file that should be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices before the final electrical test operations. this w ill ensure proper device operation in the end application. pin 9, 5v pin 7, 10v pin 5, reserved pin 3, gnd pin 1, gnd pin 6, mr# pin 4, sda pin 2, scl pin 8, reserved pin 10, reserved top view of straight 0.1" x 0.1 closed-side connector. smx3200 interface cable connector. 9 7 5 3 1 10 8 6 4 2 smm605 sda scl vdd_cap gnd 0.1 f positive supply common ground d1 1n4148 figure 10? smx3200 programmer i 2 c serial bus connections to program the smm605. the smm605 has a write protect pin (wp# input) which when, asserted, prev ents writing to the configuration registers and ee memory. in addition, there is a configuration regist er lock bit which, once programmed, does not allow the configuration registers to be changed. development hardware & software
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 16 serial interface access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standar d 2-wire serial interface (i 2 c). sda is a bi-directional data line and scl is a clock input. data is clocked in on the rising edge of scl and clocked out on the falling edge of scl. all data transfers begin with the msb. during data transfers sda must remain stable while scl is high. data is transferred in 8-bit packets with an intervening clock period in which an acknowledge is provided by the device receiving data. the scl high period (t high ) is used for generating star t and stop conditions that precede and end most transactions on the serial bus. a high-to-low transition of sda while scl is high is considered a start condition while a low-to-high transition of sda while scl is high is considered a stop condition. the interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. the address byte is comprised of a 4-bit device type identifier (slave address) and a 3-bit bus address. the remaining bit indicates either a read or a write operation. refer to table 1 for a description of the address bytes used by the smm605. the device type identifier for the memory array is generally set to 1010 bin following the industry standard for a typical nonvolatile memory. there is an option to change the identifier to 1011 bin allowing it to be used on a bus that may be occupied by other memory devices. the configuration registers are grouped with the memory array and thus use 1010 bin or 1011 bin as the device type identifier. the command and status registers are accessible with the separate device type identifier of 1001 bin . the bus address bits a[1:0] are programmed into the configuration registers. bu s address bit a[2] can be programmed as either 0 or biased by the a2 pin. the bus address accessed in the address byte of the serial data stream must match the setting in the smm605 and on the a2 pin. any access to the smm605 on the i 2 c bus will temporarily halt the monitoring function. the smm605 halts the monitor function from when it acknowledges the address byte until a va lid stop is received. write writing to the memory or a configuration register is illustrated in figures 11, 12, 13, 17 and 18. a start condition followed by the address byte is provided by the host; the smm605 responds with an acknowledge; the host then responds by sending the memory address pointer or configur ation register address pointer; the smm605 responds with an acknowledge; the host then clocks in on byte of data. for memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. after the last byte is clocked in and the host receives an acknowledge, a stop condition must be issued to initiate the nonvolatile write operation. read the address pointer for the configuration registers, memory, command and status registers must be set before data can be read from the smm605. this is accomplished by issuing a dummy write command, which is simply a write command that is not followed by a stop condition. the dummy write command sets the address from which data is read. after the dummy write command is issued, a start command followed by the address byte is sent from the host. the host then waits for an acknowledge and then begins clocking data out of the slave device. the first byte read is data from the address pointer set during the dummy write command. additional bytes can be clocked out of consecutive addresses with the host providing an acknowledge after each byte. after the data is read from the desired registers, the read operation is terminated by the host holding sda high during the acknowledge clock cycle and then issuing a stop condition. refer to figures 14, 16, 19 and 21 for an illustration of the read sequence. i 2 c programming information
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 17 write protection the smm605 powers up into a write protected mode. writing a code to the volatile write protection register can disable the write protection. the write protection register is located at address 87 hex of slave address 1001 bin . writing 0101 bin to bits [7:4] of the write protection register allow writes to the general-purpose memory while writing 0101 bin to bits [3:0] allow writes to the configuration registers. the write protection can re- enable by writing other codes (not 0101 bin ) to the write protection register. writing to the write protection register is shown in figure 11. configuration registers the majority of the configuration registers are grouped with the general-purpose memory located at either slave address 1010 bin or 1011 bin . the bus address bits, a[1:0], used to differentiate the general-purpose memory from the configuration registers are set to 11 bin . bus address bit a[2] can be programmed as either 0 or biased by the a2 pin. two additional configuration registers are located at addresses 83 hex and 84 hex of slave address 1001 bin . writing and reading the configuration registers is shown in figures 14 and 16. note: configuration writes or reads of registers 00 hex to 0f hex should not be performed while the smm605 is margining. general-purpose memory the 4k-bit general-purpose memory is located at either slave address 1010 bin or 1011 bin . the bus address bits, a[1:0], used to differentiate the general- purpose memory from the configuration registers are set to 00 bin for the first 2k-bits and 01 bin for the second 2k-bits. bus address bit a[2] can be programmed as either 0 or biased by the a2 pin. the word address must be set each time the memory is accessed. memory writes and reads are shown in figures 17, 18 and 19. command and status registers the command and status registers are located at slave address 1001 bin . writes and reads of the command and status registers are shown in figures 20 and 21. graphical user interface (gui) device configuration ut ilizing the windows based smm605 graphical user interface (gui) is highly recommended. the software is available from the summit website ( www.summitmicro.com ). using the gui in conjunction with this datasheet and application note 40 simplifies the process of device prototyping and the interaction of the various functional blocks. a programming dongle (smx3200) is available from summit to communicate with the smm605. the dongle connects directly to the parallel port of a pc and programs the device through a cable using the i 2 c bus protocol. slave address bus address register type 1001 bin a2 a1 a0 write protection register, command and status registers, two configuration registers 1010 bin or 1011 bin a2 0 0 1 st 2-k bits of general-purpose memory a2 0 1 2 nd 2-k bits of general-purpose memory a2 1 1 configuration registers table 1 - address bytes used by the smm605. i 2 c programming information (continued)
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 18 s t a r t w a c k master slave a c k configuration register address = 87 hex 1 0000111 0 1010101 s t o p data = 55 hex a c k 1 0 0 1 a 2 bus address a 1 a 0 5 hex unlocks general purpose ee 5 hex unlocks configuration registers write protection register address 8 hex 7 hex figure 11 ? write protection register write s t a r t 1 a 2 bus address w a c k master slave a c k 1 1 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k figure 12 ? configuration register byte write s t a r t 1 a 2 bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) 1 1 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k figure 13 ? configuration register page write i 2 c programming information (continued)
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 19 s t a r t 1 a 2 bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) 1 1 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t 1 r a c k a 2 bus address 1 1 s a 0 0 1 a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) figure 14 - configuration register read s t a r t w a c k master slave a c k configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k 1 0 0 1 a 2 bus address a 1 a 0 figure 15 - configuration register with slave address 1001 bin write s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) 1 0 0 1 a 2 bus address a 1 a 0 1 0 0 1 a 2 bus address a 1 a 0 figure 16 - configuration register with slave address 1001 bin read i 2 c programming information (continued)
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 20 s t a r t 1 bus address w a c k master slave a c k 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k 0 a 2 0 / 1 figure 17 ? general purpose memory byte write bus address 0 a 2 0 / 1 s t a r t 1 w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) 0 1 s a 0 configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k figure 18 - general purpose memory page write s t a r t 1 w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) 0 1 s a 0 memory address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t 1 r a c k 1 s a 0 0 a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) bus address 0 a 2 0 / 1 bus address 0 a 2 0 / 1 figure 19 - general purpose memory read i 2 c programming information (continued)
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 21 s t a r t w a c k master slave a c k command and status register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k 1 0 0 1 a 2 bus address a 1 a 0 figure 20 ? command and status register write s t a r t w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) command and status register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) 1 0 0 1 a 2 bus address a 1 a 0 1 0 0 1 a 2 bus address a 1 a 0 figure 21 ? command and status register read i 2 c programming information (continued)
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 22 default configuration registe r settings ? smm605fc-890 register contents register contents register contents r00 0d r18 00 r40 0d r01 84 r19 00 r41 ab r02 0e r30 0d r42 0e r03 00 r31 64 r43 2d r04 0e r32 0d r44 0e r05 80 r33 da r45 c7 r06 0e r34 0e r46 0e r07 c7 r35 46 r47 f1 r08 0f r36 0e r48 0f r09 55 r37 a2 r49 92 r0a 0b r38 0f r4a 0b r0b 27 r39 20 r4b 70 r0c 7f r3a 0f r83 00 r0d 3f r3b d9 r84 03 r0e 04 r3c 00 r86 03 r0f 00 r3d 12 r87 ff r3e 50 rc1 the default device ordering number is smm605fc-890, is programmed as described above and tested over the commercial temperature range. application note 40 contains a complete description of the windows gui and the default settings of each of the 48 individual configuration registers.
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 23 package a b pin 1 indicator inches (millimeters) 0.002 - 0.006 (0.05-0.15) max. 0.047 (1.2) 0.037 - 0.041 0.95 - 1.05 0.018 - 0.030 (0.45 - 0.75) 0.039 (1.00) 0.02 (0.5) bsc 0.007 - 0.011 (0.17 - 0.27) detail "a" detail "b" (b) (a) (a) 0.354 (9.00) bsc 0.276 (7.00) bsc (b) 48 pin tqfp package 0 o min to 7 o max ref jedec ms-026 ref
smm605 preliminary information summit microelectronics, inc 2064 2.1 12/16/2011 24 part marking summit smm605fl tyww pin 1 nnnn summit part number part number suffix (contains customer specific ordering requirements) drawing not to scale 100% sn, rohs compliant mnyyww assembly identification code test identification code ordering information notice note 1 - this is a preliminary information data sheet that describes a summit product current ly in pre-production with limited characterization. summit microelectronics, inc. reserves the ri ght to make changes to the products cont ained in this publication in order to impr ove design, performance or reliability. summit microelec tronics, inc. assumes no responsibility for the use of any circuits described herei n, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and sche dules contained herein reflect representative operating parameters, and may vary depending upon a user?s specific application. while the inform ation in this publication has been carefully checked, summi t microelectronics, inc. shall not be liabl e for any damages arising as a result o f any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expe cted to cause any failure of either syst em or to significantly affect their sa fety or effectiveness. products are not authorized for use in such applications unless su mmit microelectronics, inc. receiv es written assurances, to i ts satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. revision 2.1 - this document supersedes all previous versions. please check the su mmit microelectronics inc. web site at www.summitmicro.com for data sheet updates. ? copyright 2003 summit microelectronics, inc. programmable power for a green planet? adoc tm is a trademark of summit microelectronics, inc., i 2 c is a trademark of philips corporation. smm605 f nnnn package f=48 lead tqfp part number suffix summit part number specific requirements are contained in the suffix such as commercial or industrial temp range, hex code, hex code revision, etc. l environmental attribute c temp range c=commercial blank=industrial

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